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In this MagmaWire we look at the push toward designing bigger chips. Remember when the prospect of a 10-million gate design was a big deal? That is so yesterday. Today designers are targeting 40-million-gate designs, looking toward designs of 100-million gates, and some SoC designers’ roadmaps point toward 1 billion gates. The challenges are many, and we know leading-edge design is both costly and resource intensive. Magma CEO Rajeev Madhavan offers his perspective on these challenges. Also included are the following articles that provide more information about the latest features in Magma products that enable the design of large chips:
The traditional, predominately interactive approach to chip planning and design feasibility analysis has become too time consuming and inaccurate for large systems on a chip. , Magma’s hierarchical design planning solution, provides designers the ideal combination of advanced capabilities and broad flexibility, letting them apply their expertise to critical issues while automating significant portions of the flow.
Recently announced enhancements in Hydra 1.1 give the macro placer improved capacity with support for thousands of macros, improved congestion and timing awareness for both inter-block and intra-block communication, and extended relative placement constraint support.
The shaper now supports any mix of design styles including channel style, near abutment and full abutment. The slack-proportionate time budgeting and incremental re-budgeting capabilities deliver more accurate budgets than traditional methods. Hydra 1.1's new clock planning technology supports both top-down and bottom-up clock tree construction. With native support for hierarchy and multi-threading, Hydra 1.1’s timing-driven global router constructs the signal topologies required for pin assignments and accurate congestion analysis during the chip planning stage.
Read the recent ESNUG posting where Open-Silicon describes how they saved 12 to 14 man-weeks using Hydra.
To learn more about how Hydra delivers better floorplans and faster results for the biggest designs, download the “Got Design Planning?” white paper.
Design teams are facing increasing pressure to build larger, more complex chips with fewer resources and shorter delivery schedules. Talus® Design and Talus RTL are fast, high-capacity synthesis solutions that optimize for power, area and timing, and generate both gate-level netlists and Magma Volcano™ databases for handoff. Talus RTL provides a complete RTL-to-netlist synthesis solution while Talus Design adds physical synthesis capabilities to deliver higher levels of predictability and performance. Unlike traditional synthesis tools, a single Talus Design or Talus RTL license provides a comprehensive synthesis solution with seamless scan insertion and scan optimization that supports VHDL, Verilog and System Verilog. New RTL-to-GDSII reference flows for leading IP providers including ARM, MIPS and Imagination Technologies are available in version 1.1 of Talus Design and Talus RTL. The reference flows and enhancements make it easier to get better results out of the box. For more details on recent upgrades, get the new Talus Design and Talus RTL data sheets.
At the 28-nanometer node designs are expected to exceed 100 million gates, have 15 or more process, voltage and temperature (PVT) corners, supply voltages under 1V and shorter design cycles. To handle the size and complexity of these ICs, design teams must reevaluate every aspect of their design methodology, including resource planning, design architecture and final timing sign-off solutions. In this article recently featured in Chip Design, Magma’s Bob Smith outlines the limitations of conventional static timing analysis (STA) tools and what the next generation of STA tools will need to have to meet designers’ needs for higher capacity, greater accuracy and faster turnaround time.
Read more.
Meeting manufacturing requirements at 65 nm and below requires running sign-off physical verification (DRC/LVS) concurrently with place and route. Magma has pioneered this capability with Talus qDRC and Talus qLVS, which integrate the sign-off Quartz physical verification products into Talus.
Integrating physical verification into the RTL-to-GDSII flow allows users to avoid costly last-minute iterations between GDS-based DRC/LVS tools and Talus, decreasing project cycles by weeks. Talus users are also able to improve timing convergence and better manage power by using Talus qDRC’s timing-driven pattern-based fill capability. Because Talus qDRC and Talus qLVS are based on the popular sign-off Quartz DRC and Quartz LVS products, they provide full sign-off capabilities with turnaround times up to 10x faster than legacy tools.
Learn more, download the “Moving Sign-off into the Implementation Flow with Talus qDRC” white paper.
Rajeev MadhavanChairman & CEO, Magma Design Automation
Remember when the prospect of a 10-million-gate design was a big deal? That was yesterday. Today the market is actively targeting 40-million-gate designs with a view towards 100-million-gate designs. And, on the roadmap of some of the largest system-on-chip (SoC) providers is the 1-billion-gate design. The expectation is that all of this can be achieved without massive increases in resources and schedules and that performance can be increased while power consumption is decreased. Naturally, many designers are worried about how to meet these expectations. It is no surprise that the challenges of SoC design continue to multiply. Digital design is being driven by complexity. The table below compares the typical design at 250 nanometer (nm) with the designs being anticipated at 32 nm. The challenges are clear – leading-edge digital design is not for everyone because it is both costly and resource intensive.
In addition, mixed-signal SoCs are growing rapidly, and, in fact, it could be argued that all SoC designs contain at least some analog components and should properly be called mixed-signal. Analog design remains as one of the least-automated components of SoC design. Typically handcrafted by expert designers, analog components and blocks do not provide the same ease of re-use as digital blocks. Migration from one technology node to another, or re-targeting an analog block to a different design, is a costly, time-consuming process. Design optimization for better area, performance and/or power is also an almost exclusively manual process that has been further complicated by the variability challenges presented by 12 inch fabs. The chip-level integration of the analog and digital components on a mixed-signal SoC is another area that has typically been time consuming and error prone. More often than not, the analog blocks that must be integrated reside on an entirely different database than the digital components. Our challenge as an EDA vendor is to lower the barrier by providing increased productivity and delivering better performance so that more companies can take advantage of the benefits of the newer process nodes.
So what are we doing to address these issues? More than 18 months ago it became clear to us that a big leap in productivity for digital design would be needed. At the same time, we recognized that mixed-signal SoC was becoming the norm and that solving just the digital challenges would not be enough. To address these challenges we kicked-off and invested in a wide-ranging internal development program that we referred to as “Sahara.” On the digital side, our goal was to tackle 40-million-gate designs where our customers were experiencing – or anticipating – 30- to 42-week turnaround times. Our goal was to reduce the turnaround time by 3x. On the mixed-signal front, our goal was to deliver a more automated analog design system that shared the same database as our digital system to eliminate the headaches of mixed-signal SoC reuse, migration, and chip integration and finishing.
I am pleased to report that we have made excellent progress towards these goals. Our latest version of the Talus® system offers full multi-threading for faster turnaround of very large designs – without comprising design performance. Additional technology being added will allow designers to tackle much larger individual blocks in the 8-million- to 40-million-gate range, with faster turnaround times and without having to expand the design team or resources. Are your designs even larger? No problem, the latest release of Hydra™, our advanced design planner, delivers much faster design and chip planning through automation. The technologies in Hydra will be used well beyond the 40-million-gate goal to deliver hierarchical solutions for designs of 100 million gates and beyond.
Finally, the icing on the digital implementation cake is a new high-capacity timing and extraction technology we have developed that delivers an order-of-magnitude improvement in static timing analysis throughput (without requiring new hardware purchases) with SPICE-level accuracy. I’ll talk more on this in a future edition of MagmaWire… On the analog side, the investment resulted in our release of the Titan™ platform. Titan represents the next generation in automated analog/mixed-signal design and implementation. More recently, the platform was expanded to include the Titan Analog Design Accelerator (ADX). Titan ADX automates top-down analog design and implementation and accelerates analog design and block reuse, optimization and porting. Titan’s ability to efficiently optimize and port analog designs has been demonstrated at both Panasonic and TSMC and the technology is currently undergoing engagements at 7 of the world’s Top 20 semiconductor companies. Panasonic is using Titan ADX to create a methodology for circuit optimization that allows a variety of architectures to be optimized very quickly. With Titan ADX, Panasonic can reduce area, minimize power consumption and avoid design iterations on large, complex analog designs – achieving in days what used to take weeks.
Coupling the Titan technology with the simulation breakthroughs we delivered in FineSim and FineSim Pro is allowing designers to truly accelerate analog/mixed-signal design. The development of this technology has been a very interesting challenge that I will talk about in a future MagmaWire…
So, there’s no need to worry about how to complete big chips. At Magma we’ve done the work needed to create the most automated solution available today precisely so you can design and implement large, mixed-signal SoCs. But this is not the end of our investment – chip design is a dynamic endeavor with new challenges arising constantly. We will continue to invest heavily in providing the solutions that help designers create increasingly complex chips.