TSMC Standard Cell Libraries — 65NM

Other libraries: 40NM — 45M — 65NM — 90NM — 130NM — 150NM

Contact foundrysupport@magma-da.com with any questions.

Process Name	Library Name	Description	Version
CLN65LP	TCBN65LP	TSMC 65nm Logic Low-Power 1.2/2.5V process, 0.20um x-pitch, Standard Vt, 9-track, Raw gate density = 854 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 0.8V +/- 10%, CCS timing/noise model is included	200b
	TCBN65LPHVT	TSMC 65nm Logic Low-Power 1.2/2.5V process, 0.20um x-pitch, High Vt, 9-track, Raw gate density = 854 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 0.8V +/- 10%, CCS timing/noise model is included	200b
	TCBN65LPLVT	TSMC 65nm Logic Low-Power 1.2/2.5V process, 0.20um x-pitch, Low Vt, 9-track, Raw gate density = 854 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 0.8V +/- 10%, CCS timing/noise model is included	200b

	TCBN65LPCG	TSMC 65nm low-power process (1P9M, core 1.2V), 9-Track, Coarse-grain MTCMOS library, Standard-Vt , Include special cell for 1) retention flip-flop cell, 2) always on cell	140b
	TCBN65LPCGHVT	TSMC 65nm Low-power process (1P9M, core 1.2V), Coarse-grain MTCMOS library, High-Vt total 20 cells, Include special cell for 1) power switch header cell, 2) retention flip-flop cell, 3) always on cell	140b
	TCBN65LPCGLVT	TSMC 65nm Low-power process (1P9M, core 1.2V), 9-Track, Coarse-grain MTCMOS library, Low-Vt , Include special cell for 1) retention flip-flop cell, 2) always on cell	140b

	TCBN65LPHPBWP	TSMC 65nm Logic Low-Power 1.2/2.5V process, 0.20um x-pitch, Standard Vt, 10-tracks, Support multi-Vdd design , low-voltage range is 0.8V +/- 10%, CCS timing/noise model is included	140b
	TCBN65LPHPBWPHVT	TSMC 65nm Logic Low-Power 1.2/2.5V process, 0.20um x-pitch, High Vt, 10-tracks, Support multi-Vdd design , low-voltage range is 0.8V +/- 10%, CCS timing/noise model is included	140b
	TCBN65LPHPBWPLVT	TSMC 65nm Logic Low-Power 1.2/2.5V process, 0.20um x-pitch, Low Vt, 10-tracks, Support multi-Vdd design , low-voltage range is 0.8V +/- 10%, CCS timing/noise model is included	140b
	TCBN65LPHPBWPCG	TSMC 65nm Logic Low-Power 1.2/2.5V process, 0.20um x-pitch, Standard Vt, 10-tracks, Support multi-Vdd design , low-voltage range is 0.8V +/- 10%, CCS timing/noise model is included	140a
	TCBN65LPHPBWPCGHVT	TSMC 65nm Logic Low-Power 1.2/2.5V process, 0.20um x-pitch, High Vt, 10-tracks, Support multi-Vdd design , low-voltage range is 0.8V +/- 10%, CCS timing/noise model is included	140a
	TCBN65LPHPBWPCGLVT	TSMC 65nm Logic Low-Power 1.2/2.5V process, 0.20um x-pitch, Low Vt, 10-tracks, Support multi-Vdd design , low-voltage range is 0.8V +/- 10%, CCS timing/noise model is included	140a

	TCBN65LPBWP12T	TSMC 65nm Logic Low-Power 1.2/2.5V process, 0.20um x-pitch, Standard-Vt, 12-track, Raw gate density = 854 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 0.8V +/- 10%	140c
	TCBN65LPBWP12THVT	TSMC 65nm Logic Low-Power 1.2/2.5V process, 0.20um x-pitch, High-Vt, 12-track, Raw gate density = 854 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 0.8V +/- 10%	140c
	TCBN65LPBWP12TLVT	TSMC 65nm Logic Low-Power 1.2/2.5V process, 0.20um x-pitch, Low-Vt, 12-track, Raw gate density = 854 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 0.8V +/- 10%	140c

	TCBN65LPBWP12TCG	TSMC 65nm Low-power process (1P9M, core 1.2V), Coarse-grain MTCMOS library, Standard-Vt total 20 cells, Include special cell for 1) power switch header cell, 2) retention flip-flop cell, 3) always on cell	140a
	TCBN65LPBWP12TCGHVT	TSMC 65nm Low-power process (1P9M, core 1.2V), Coarse-grain MTCMOS library, High-Vt total 20 cells, Include special cell for 1) power switch header cell, 2) retention flip-flop cell, 3) always on cell	140a
	TCBN65LPBWP12TCGLVT	TSMC 65nm Low-power process (1P9M, core 1.2V), Coarse-grain MTCMOS library, Low-Vt total 20 cells, Include special cell for 1) power switch header cell, 2) retention flip-flop cell, 3) always on cell	140a

	TCBN65LPBWP7T	TSMC 65nm Logic 1.2V/2.5V Low power process (1P9M, core 1.2V), Standard Vt, 7-track library. 0.20um x-pitch, total 644 cells (include 620 base cells, 9 level shifter cells, 6 isolation cells and 8 filler cells, 1 tapcell), Raw gate density = 1020 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 1.0V +/- 10%, CCS timing model is included	141a
	TCBN65LPBWP7THVT	TSMC 65nm Logic 1.2V/2.5V Low power process (1P9M, core 1.2V), High Vt, 7-track library. 0.20um x-pitch, total 644 cells (include 620 base cells, 9 level shifter cells, 6 isolation cells and 8 filler cells, 1 tapcell), Raw gate density = 1020 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 1.0V +/- 10%, CCS timing model is included	141a
	TCBN65LPBWP7TLVT	TSMC 65nm Logic 1.2V/2.5V Low power process (1P9M, core 1.2V), Low Vt, 7-track library. 0.20um x-pitch, total 644 cells (include 620 base cells, 9 level shifter cells, 6 isolation cells and 8 filler cells, 1 tapcell), Raw gate density = 1020 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 1.0V +/- 10%, CCS timing model is included	141a

	TCBN65LPG	TSMC 65nm Logic LP-based TGO with dual-core 1p9m 1/1.2/2.5V process, 0.20um x-pitch, Standard Vt, total 846 cells (include 816 base cells, 12 level shifter cells, 8 isolation cells and 10 filler cells), 9-tracks, Raw gate density = 854 Kgate/mm^2	130b
	TCBN65LPGHVT	TSMC 65nm Logic LP-based TGO with dual-core 1p9m 1/1.2/2.5V process, 0.20um x-pitch, High Vt, total 846 cells (include 816 base cells, 12 level shifter cells, 8 isolation cells and 10 filler cells), 9-tracks, Raw gate density = 854 Kgate/mm^2	130b
	TCBN65LPDF	TSMC 65LP process (core voltage = 1.0V), dual-FF,Standard-VT, 0.20um x-pitch, 9-tracks, Raw gate density = 854 Kgate/mm^2	140a
	TCBN65LPDFHVT	TSMC 65LP process (core voltage = 1.0V), dual-FF,High-VT, 0.20um x-pitch, 9-tracks, Raw gate density = 854 Kgate/mm^2	140a
	TCBN65LPDFLVT	TSMC 65LP process (core voltage = 1.0V), dual-FF,Low-VT, 0.20um x-pitch, 9-tracks, Raw gate density = 854 Kgate/mm^2	140a

CLN65GP	TCBN65GPLUS	TSMC 65nm Logic 1.0V/1.8V GPLUS process (1P9M, core 1.0V),Standard-Vt,9-track.Includes level shifter and isolation cell for multi-vdd designs.	140b
	TCBN65GPLUSHVT	TSMC 65nm Logic 1.0V/1.8V GPLUS process (1P9M, core 1.0V),High-Vt,9-track.Includes level shifter and isolation cell for multi-vdd designs.	140b
	TCBN65GPLUSLVT	TSMC 65nm Logic 1.0V/1.8V GPLUS process (1P9M, core 1.0V),Low-Vt,9-track.Includes level shifter and isolation cell for multi-vdd designs.	140b

	TCBN65GPLUSCG	TSMC 65nm Generic-plus process (1P9M, core 1.0V), Coarse-grain MTCMOS library, Standard-Vt	140b
	TCBN65GPLUSCGHVT	TSMC 65nm Generic-plus process (1P9M, core 1.0V), Coarse-grain MTCMOS library, High-Vt	140b
	TCBN65GPLUSCGLVT	TSMC 65nm Generic-plus process (1P9M, core 1.0V), Coarse-grain MTCMOS library, Low-Vt	140b

	TCBN65GPLUSHPBWP	TSMC 65nm Logic 1.0V/1.8V GPLUS process (1P9M, core 1.0V), 0.20um x-pitch, Standard-Vt, 10-tracks, Tapless cell layout structure, Support multi-Vdd design , low-voltage range is 0.8*Vdd +/- 10%. Includes level shifter and isolation cell for multi-vdd designs.	140a
	TCBN65GPLUSHPBWPHVT	TSMC 65nm Logic 1.0V/1.8V GPLUS process (1P9M, core 1.0V), 0.20um x-pitch, High-Vt, 10-tracks, Tapless cell layout structure, Support multi-Vdd design , low-voltage range is 0.8*Vdd +/- 10%. Includes level shifter and isolation cell for multi-vdd designs.	140a
	TCBN65GPLUSHPBWPLVT	TSMC 65nm Logic 1.0V/1.8V GPLUS process (1P9M, core 1.0V), 0.20um x-pitch, Low-Vt, 10-tracks, Tapless cell layout structure, Support multi-Vdd design , low-voltage range is 0.8*Vdd +/- 10%. Includes level shifter and isolation cell for multi-vdd designs.	140a

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