Titan FlexCell Libraries

Titan FlexCell libraries provide modular, process-independent building blocks that raise the level of abstraction for analog design, enabling reuse and rapid design exploration with Titan ADX.

Design abstraction in analog design is typically done at a very low level, most often rising no higher than the vendor transistor and PCell models. Even though topologies for basic functions such as op amps, band gaps and VCOs may not change, lacking automation for optimization, each block instance for every new design must be re-created.

Titan FlexCell libraries are ideal starting points for raising the level of IP reuse for analog design. Each FlexCell represents a specific topology for a building block common to analog developments. Users can build unique designs by selecting their preferred topology for various building blocks from the FlexCell library, combining the functions to create the higher-level analog design, then setting the desired constraints for the overall design and optimizing the results using Titan ADX. This raises the level of abstraction for analog design from PCells to the building-block level.

Titan FlexCell Libraries raise the level of abstraction for analog design to enable reuse and
constraint-based design optimization

What is a FlexCell? 

FlexCells are modular, reusable IP building blocks for analog design. The cells include all the information necessary to optimize common functions using Titan ADX to generate custom analog designs.

Circuit Model
The analog function is described as a set of equations in an “.m” file. This file uses a MATLAB-style syntax to describe the circuit function, constraints and topology. Source files are provided with the library, allowing designers to easily reuse and generate custom FlexCells.

Physical Model
Each FlexCell includes sets of constraints to guide the floorplanning and placement of the design layout. These features include process-independent placement requirements such as relative cell positioning of differential pairs.

Schematic
The FlexCell includes a transistor-level schematic of the circuit design. Schematics may be viewed in existing design environments, or using the Titan Schematic Editor.

Testbenches 
A complete testbench schematic is included for each FlexCell circuit to provide stimulus and analysis of the design functionality and performance.

Basic and Advanced Titan FlexCells 

Titan FlexCells are provided in two libraries, one includes basic analog building blocks, the other, more advanced analog circuit functionality. These libraries provide comprehensive support for the functional blocks commonly used in analog designs. The libraries are provided with full source files and are open and editable, allowing users to quickly copy and edit the files to create custom libraries of FlexCells that meet special requirements, topologies and constraints.

The following list describes some of the building blocks currently available in the Titan FlexCell libraries. The list of available IP is growing fast, so contact your Magma representative for a complete list.

Basic Library
• Op Amps
  – Single-ended: single-stage, two-stage, folded-cascode, telescopic, current mirror, and  
     two-stage FC with class AB output.
  – Differential: folded-cascode, telescopic, telescopic two-stage, folded-cascode two-stage and folded-cascode 
     two-stage with wide-swing output.
  – NMOS, PMOS and CMOS inputs (where applicable). 
  – Output compensated, miller comp., cascode comp. and mixed cascode/miller comp.

• Voltage Regulator (LDO) – several topologies
  – Basic LDO with on-chip/off-chip load
  – Adaptive bias LDO with on-chip/off-chip load

• Bandgap 
  – Current-mode bandgap for 1V operation
  – Voltage-mode bandgap for higher Vdd standard topology

Advanced Library
• Linear Equalizer
  – Programmable source resistor and capacitor
  – Optimized for channel loss (minimize jitter due to ISI)
  – Single and multi-stage options

• Pipelined ADC
  – Includes amplifiers, switches and capacitive feedback (stage).
  – Includes system-level optimization: area/power vs. input range, area/power vs. bits-per-stage and
     settling time vs. power.

• Sigma-Delta ADC
  – Includes amplifiers, switches and capacitive feedback (stage).
  – System-level optimization with simplified blocks or transistor-level blocks

• Ring Oscillator PLL
  – Includes multiple VCO, CP and LF topologies
  – With or without replica bias
  – Single-ended/differential, single-phase/multi-phase oscillator options
  – SERDES CDR, clock generation or clock deskew applications

• PCIE/SATA/XAUI Drivers
  – Mixed inverter-based/CML driver with pre-emphasis and rise/fall time control