Titan Mixed-Signal Design Platform

Titan is the industry’s first design platform to truly integrate analog and digital design to deliver a complete custom design implementation and verification platform for mixed-signal integrated circuits.

Analog designers now have a choice when it comes to design environments. The Titan Mixed-Signal Design Platform is a comprehensive, state-of-the-art design platform specifically tuned to meet the current and future needs of analog/mixed-signal designers. The Titan platform delivers first-time-correct, predictable mixed-signal designs without sacrificing performance, while shortening the design process by weeks. With automated mixed-signal assembly and verification, Titan provides an order-of-magnitude productivity improvement over other tool flows.

The Titan Mixed-Signal Design Platform is a unified mixed-signal design cockpit with a very high capacity and a very fast database access mechanism. Titan comprises user-friendly full-custom schematic and layout editors, an analog simulation environment integrated with the FineSim simulator, correct-by-design schematic-driven layout and integration with Magma’s tools for physical verification and digital implementation. By fully embedding Talus for digital design, Titan combines full-custom analog design tools with a digital flow for high-level mixed-signal chip design efficiency.

Titan also includes an integrated solution for mixed-signal chip finishing. The unprecedented level of integration and automation provided by Titan enables a significant increase in productivity by eliminating the potentially time-consuming and difficult iterations between traditional custom layout and standard-cell implementation systems. To further streamline the design process, Titan supports OpenAccess and emerging industry integration standards.

Titan Mixed-Signal Design Platform Features

• Provides a complete mixed-signal design cockpit that allows the user to design from specification to GDSII in a single environment
• Platform capabilities include schematic editor, layout editor, analog simulation environment and schematic-driven layout
• Layout-aware schematic design integrates physical implementation with design intent
• Provides highest speed and capacity to handle even the largest mixed-signal designs from the top level
• Supports legacy customer data and is easily integrated with existing flows
• Tight integration with Magma’s Talus digital implementation, FineSim circuit simulation and Quartz DRC and Quartz LVS physical verification tools eases adoption
• Open architecture, compliant with industry standards for PDK compatibility – supports TSMC iPDK and other industry formats
• Enhanced by Titan Accelerators enabling analog IP reuse, rapid design exploration, shape-based routing and automated process porting

Titan Mixed-Signal Platform Capabilities 

Chip Finishing
In traditional flows, chip finishing is often performed by hand, and it includes a number of tasks that occur right before the chip tape out. Magma’s chip integration and finishing solution is fully automated and seamlessly integrated with the Talus digital implementation flow, eliminating the potentially long and painful loops between existing custom layout and standard cell implementation systems. Titan Chip Finishing includes all the capabilities of Titan Mixed-Signal Design Platform plus Titan SBR, the Titan Accelerator that provides high-performance shape-based routing.

  Titan Schematic Editor (SE)

• Comprehensive, powerful, easy-to-use feature set driven by menus and hotkeys
• Auto-wiring capability
• Top-down design capability
• Advanced search and replace
• Full support for buses and bundles
• Support for multi-sheet schematics
• Inherited connections
• Easy hierarchy traversal
• Custom netlist generation
• Support for various formats, including HDL and Verilog
• On-canvas editing

Titan Analog Simulation Environment (ASE)

• Complete SPICE simulation environment for analog circuits
• Interactive GUI and comprehensive scripting support
• Supports simulation job distribution (LSF, SGE)
• Easy simulator-independent test-bench creation
• Specification-driven environment with complete characterization setup
• Integrated with Titan SE for design analysis and debug such as DC operating point, back annotation and probing
• Intuitive post-processing capability
• Advance capabilities include corner simulation, parametric sweep and Monte Carlo simulation to characterize the design
• Test reusability including DUT-based test bench mapping

Titan Schematic-Driven Layout (SDL)

• Full connectivity-aware layout creation using any language pCells including those from IPL or iPDK
• Ability to control the layout hierarchy creation
• Bi-directional cross-probing between layout and schematic
• Check and update of layout with regard to schematic
• Support for pattern-based device module creation
• Ability to view opens and shorts
• Flyline control options

Titan Layout Editor (LE)

• Comprehensive, powerful, easy-to-use feature set driven by menus and hotkeys
• High capacity and speed
• Full custom creation and editing options for shapes
• Controls for viewing and selecting objects and layers
• Editing in place and hierarchy traversal options
• Net finding and tracing capabilities
• Advanced search and replace
• Grouped path and guard ring creation
• Advanced object alignment features
• Wiring and bus wiring capabilities
• Live DRC

Support for Legacy Data and Formats

• Fully open architecture
• Support for read and write of OpenAccess database
• Support for industry-standard formats including GDSII, LEF/DEF, SPICE and Verilog
• Migrates legacy data
• Support for any language pCells and Python pyCells
• Support for the TSMC iPDK libraries for industry-wide data sharing

Supported Platforms
• Linux 32 and 64 bit