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Talus® qDRC is an integrated physical design verification tool for direct use during implementation. Using foundry-certified design-rule runsets, Talus qDRC increases productivity by providing sign-off quality DRC from within the implementation environment. Visibility to reference-level IP views with all GDSII layers makes debugging easy. The incremental mode handles ECOs in seconds, operating on only those portions of the design that changed.
Designs at 65 nanometer (nm) and below are exposing the inadequacies of the old design method of streaming out GDSII for final DRCs and LVS checks. The longer turnaround times, late detection of serious problems and the error-prone effects of moving in and out of different tools create delays and increase costs.
With traditional methods, problems are uncovered late, often cause time-consuming design iterations. A mismatch between the LEF representation and the GDSII of the intellectual property (IP) reference library, a power grid open or short, I/O alignment issues, or standard-cell fill errors are often found late and require reworking placement and routing.
Talus qDRC is an implementation-based physical verification tool that runs during placement and routing to immediately identify and correct problems. At each point in the flow, the DRC checks are run, resulting in sign-off-clean designs produced directly by the implementation environment.
DRC sign-off during implementation is the emerging paradigm for increasing productivity. As the design moves from floorplanning to initial layout and placement, ongoing design rule checking guarantees that the I/O ring and power-mesh layout are correct. After routing, the reference views of all IP can be used to validate that there are no alignment issues. With a simple command (shown below), DRCs can be systematically run at every point in the place-and-route flow to eliminate downstream problems:
talus> check quartz drc $m This command produces powerful results. Any DRC violations are shown within the mantle/Talus environment. Debugged DRC violations are run against a certified runset for sign-off within the implementation flow. There is no need to stream out data to identify violations, the DRCs are executed efficiently with one command.
talus> check quartz drc $m
This command produces powerful results. Any DRC violations are shown within the mantle/Talus environment. Debugged DRC violations are run against a certified runset for sign-off within the implementation flow. There is no need to stream out data to identify violations, the DRCs are executed efficiently with one command.
The Talus qDRC all-layer view exposes the real DRC issue,allowing quick and easy fixes in the Volcano.
Talus qDRC is certified for reference flows supported by the leading foundries. Magma and the foundries collaborate to maintain current design rule runset support for all widely used process nodes. Talus qDRC users can obtain those rule sets from the foundries and run them against their designs during implementation. Talus qDRC is capable of calling runsets from other DRC tools to bring those decks into the implementation flow to test against the design.
One of the major benefits of using Talus qDRC is that it executes from within the Talus environment. An incremental operation on the design data no longer requires a full DRC check on the entire design database. Changes are tracked so that only modified parts of the design are analyzed, saving hours of unnecessary runtime. Incremental DRC delivers immediate feedback on changes as they are made and commits instantaneous DRC corrections to the database. Talus qDRC’s incremental mode is not run as a post-processing step; it is fully incremental within the design database. Not only is debugging incremental; the entire design flow is incremental. ECO changes are validated in seconds.
Talus qDRC brings in all layers during debugging. The graphical representation of each error location is available to facilitate systematic correction.
Talus qDRC highlights errors for correction. A spacing violationis shown and easy fixes in the Volcano. highlighted in red.
A filler cell is added to correct the DRC error. Correctionsare made incrementally with Talus qDRC.
In traditional verification flows, many problems result from moving data out of the design database for DRC runs on external tools. Error markers produced after the design data is streamed out must be read back into the design database. Magma approaches design implementation based on a unified data model. Talus qDRC exploits the place-and-route design view and merges the reference views (all layers). Every change made is reflected and written directly into the design view. A DRC run from the foundry rule set is sign-off clean as soon as the change is committed.
Using Talus qDRC with certified foundry DRC decks inside the design implementation environment is the most effective way to produce a clean design. The incremental capability insures that corrective actions are committed quickly, lowering turnaround costs and preventing costly re-runs of other parts of the flow. Talus qDRC shortens DRC runtimes and the total time it takes to achieve a DRC-clean design. The results shorten the overall design cycle time by weeks. These quantifiable savings reduce design costs and speed time to market.
Direct Execution within Talus• Debugging and correcting inside Talus• Incremental execution on only material changes• All-layer viewing for complete design visibility• Reference views of all IP
Foundry Certified Design Rule Runsets • Updated and posted regularly• Available from foundry source• Calibrated together with the foundry
Physical Verification Sign-off• Implementation sign-off using the same design rule runset • Foundry-node optimized• User prioritized and editable
Advanced Features • Auto-fixing Tcl scripting• Debugging viewer• Summary error reporting
Inputs • IP reference views• Volcano
Outputs • GDSII
Platforms • Linux