Logic Design

Predictable path from RTL to placed gates

As design complexity increases and feature sizes shrink to 65 nanometer (nm) and below, the manufacturing defect spectrum changes and achieving design closure and time-to-market goals is more difficult. A broader range of sophisticated fault models is required to ensure sufficient test quality, and a very fast, high-capacity, predictable RTL and physical synthesis solution is needed.

Magma integrates production-proven RTL synthesis, automated macro placement, physical synthesis, timing analysis and design-for-test (DFT) capabilities to provide a predictable path from RTL to placed gates. Magma’s logic design products include:

Talus® Design, a full-chip synthesis environment that enables rapid development of RTL and chip-level constraints throughout the design process, and automates data-path synthesis and floorplan generation for prototyping.