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Analog and Mixed-Signal: Trends, Tips, Tools and ThoughtsEvery digital processor core needs data, and it comes from somewhere in an analog world. Taking in information over the air or from sensors quickly, accurately, and power efficiently is the quest for every design now. New techniques for analog and mixed-signal design are appearing with a new generation of EDA tools supporting them, and especially interesting are tools combining analog and digital flows to make designers more productive. This session of the EDA Virtual Conference presents the latest in trends and tips for analog and mixed-signal design, with insight into standards for designing with IP, ways to optimize designs for real estate and power, and ways to get better performance. Experts, including Magma’s Ashu Mauskar, describe how tools can be used to create reliable designs more quickly, and share thoughts on what designers of analog and mixed-signal devices are facing and how to get through those challenges.
System-on-Chip: Designing Faster and FasterHigh-speed digital design presents important challenges, including combining IP blocks quickly to form a system, and being sure the system performs as expected with no surprises. This session of the EDA Virtual Conference looks at the trends in interconnect technology, issues in maintaining signal integrity, on-chip instrumentation, and more ideas to create sophisticated SoC designs and get chips to market quickly. Experts, including Magma’s Bob Smith, discuss what they are seeing as clock speeds increase, tools capable of identifying issues, and ways to make sure a high-speed SoC functions right the first time.
Solving Design Challenges Visually with the Talus Visual VolcanoThe world of chip design is brutal. You have to build larger, more complex chips with fewer resources and in less time. The faster you can identify problems or determine which approach is best, the faster you can reach your design goals. Talus Vortex 1.1 includes the new Talus Visual Volcano, this visual analysis environment integrates and presents all design and analysis data via a common display, allowing you to make better design decisions faster. In this quick webinar, you’ll learn how you can accelerate design debugging and improve communication between team members.
Titan: Accelerating Analog DesignDigital circuit design experienced an astronomic productivity improvement with the advent of RTL synthesis and standard-cell libraries. Analog circuits, on the other hand, are still being designed at the transistor level where each device is hand-designed in both schematic and layout. Titan introduces a new set of tools to help full-custom circuit and layout design to reach the next level of productivity gains.
In this 10-minute web tutorial, you’ll see how Titan, an extremely fast and simulation-accurate analog circuit and design tool, uses a model-based approach to capture designer knowledge to optimize a circuit for performance, power and manufacturability.
Speed Up Multimode, Multicorner Timing Closure with Talus Vortex.At advanced technology nodes (90/65/45), physical designers must implement designs across many more operational modes and process, voltage, temperature (PVT) corners than ever before. With conventional tools, achieving timing closure requires multiple iterations and time-consuming manual work, resulting in excessively long turnaround times.View this webinar to learn more about Talus Vortex’ low-power multicorner clock tree synthesis, concurrent physical implementation across multiple modes and corners, and its quick and easy third-party sign-off integration. You will also see how Magma’s industry-first memory-resident data model provides the fastest throughput for getting advanced low-power, high-performance multicorner/multimode designs taped out fast.
ARM and Magma: Managing Low Power Designs - Library and Design FlowHandheld consumer devices are driving the demand for ICs with more functionality, higher performance, smaller package sizes and lower power requirements. At least three aspects of design implementation must be well understood to address power – library/process, architecture and tools/design flow. In this webinar, we address these three aspects as a joint presentation with the ARM® low-power architecture, ARM standard-cell libraries and Power Management Kit, and Magma’s low-power extension to the existing ARM and Magma reference methodology. View this webinar now and learn how ARM and Magma provide the low-power tools and methodology you need to help reach your design goals.
Virage Logic – Magma: Managing Power with a Complete Physical IP and Design FlowThe Virage Logic-Magma low-power reference methodology utilizes Magma’s Talus Power Pro to implement a number of power reduction techniques including support for designs with multiple supply-voltage domains, concurrent multi-VT optimization, power gating with MTCMOS, clock gating and multi-mode analysis and optimization.View this webinar and learn how Virage Logic and Magma provide the low-power tools and methodology you need to help reach your design goals.
Rajeev Madhavan Talks with John Cooley about Titan and MoreIn this interview, Rajeev announces "Titan", his new Virtuoso-killer, along with discussing Pcells, Ciranova, PDKs, Analog Artist, Talus, Mojave, QuickCap, Quartz-TLX, OA, MatLab, process migration, Sagantec, "AnalogWare", Cosmos, Pulsic, fabs, 65 nm, 45 nm, the Synopsys-Magma lawsuit, Jay Vleeschhouwer, bean counters, Cadence, and Mentor Calibre.
Managing Power and Performance with the ARM11 MPCore and Talus IC Implementation FlowEmbedded multiprocessing sub-systems are replacing uniprocessors to meet performance requirements of the latest hand-held consumer devices. These multicore systems have proven to deliver better MIPS/MHz, MIPS/mW and MIPS/mm2 than comparable uniprocessors, and to offer more effective power management without the need for expensive IC process technologies or heat removal techniques. In this webinar, we show how to implement the ARM11 MPCore using Magma’s Talus® Implementation Flow to better manage system power and boost performance. You see how the ARM11 MPCore design can be implemented with full control over power, both dynamic (via multiple-voltage-island optimization) and leakage (with power gating) using the integrated and automated low-power design capabilities within Magma’s Talus IC implementation platform.
Yield Enhancement Using Logic Mapping — a Fab PerspectiveLogicMap™, an option to YieldManager™ yield-management software, is the industry’s first commercially available software solution for correlating inline defects with failed nets in a logic device. This webinar outlines how to utilize LogicMap and Intensity Map software to find the root cause of defects within a logic device. We show how implementation of a LogicMap data infrastructure, automation of data inputs/outputs and aggressive application implementation can provide extremely successful correlations to inline defects and hit rates of defect locations for a rapid return on investment.
Talus qDRC: Eliminate Surprises with Sign-off Quality Verification Throughout the FlowShrinking geometry sizes and increasing design rule complexity require that physical verification be performed earlier in the flow. Talus qDRC makes available the sign-off accuracy and speed of Quartz DRC to every engineer currently using Talus. In this webinar, you see the necessary one-time configuration, including a handful of convenient customization options. We highlight a handful of convenient ways of browsing design rule violations, along with how to use the incremental mode, which runs only one the layers and sections of the design that have changed.