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Abstract: The paper introduces a fast floorplan method for high macro count and hard timing design. Magma talus can generate a quick placement for all macros and standard cells based on logic group, then we can use this placement info to highlight and divide appropriate “macro group”, which is faster and more reasonable than normal group method for high macro count design. For hard timing design, we can use aggressive “macro placement” method to show the critical logic group then tune the placement shape (keep critical logic close together without macro and other logic group blocking) by incremental “macro placement”. This method can lead to better timing (both WNS/TNS) and better routing result (total wire length) for our regular design.
Timing Closure Techniques for Challenging PartitionsAuthor(s): Di Ma and Vito Wu, NvidiaAbstract: Timing closure is always a major issue in high performance processors. Usual techniques such as size-up, inserting buffer and useful skew may not be sufficient to solve the violations in certain cases. This article will discuss some techniques that were used in previous deep sub micron projects. They are beyond usual techniques and may only be applied to special cases. These areas will be involved: predict potential partition boundary timing issue, incremental placement iteration, clock gating clone strategy selection, use wire delay to minimize delay difference under different timing corners.
Accelerating Analog IP Design with Parallel Spice Tools: The Design of WideBrand PLL with a Single Power SupplyAuthor(s): Zhuo Ma and Jihua Chen, Central South CAD CenterAbstract: For phase-locked loop(PLL) design, circuit simulation is a time-consuming step. Iteration Speed fully depends on how fast of each simulation cycle. A certain PLL, which employed in a type of embeded CPU, was established on 0.13μm CMOS process, with wide band reference clock from 10MHz to 100Mhz and output clock from 50MHz to 900MHz. Obversly, a lot of simulation work is needed in design course, including a hundred of simulation corner. The tradditional methods or spice tools could not handled such a huge workload in a definite time. With the help of parallel spice tool, FINESIM, a tool provided by MAGMA, the simulation phase was rapidly shortened. With this tool, a multithreading/multiprocessing method was employed, and the speed-up is over 3.
Handling Big Engineering Change Orders (ECOs) at the Post-Optimization Stage Author(s): Zhang Lei and Chandler Mei, NvidiaAbstract: In this paper, we discuss how we handle big ECOs at post-optimization stage. At post-optimization stage, most optimize steps have been done. We don’t want to redo the previous optimization steps. In order to achieve this object, we need to apply these ECOs more intelligent and affecting other things as less as possible. We’ll discuss some kind of big ECOs we met in project, and introduce how we handle them by Magma. The paper will cover adding/moving big macros at post-optimization stage, rebuilding buffer tree for reset nets and refining eco placement for big functional eco. We’ll look into these issues and compare different ways to implement it.
A Symmetrical Power Structure for the Repeated Blocks of a Hierarchical Design Author(s): Tony Ku, Global UniChipAbstract:In some ASIC, the function blocks will be instantiated in multiple times, like DDR and network design. These reused function blocks should be implemented once and then cloned the content to other blocks to reduce the implementation period. But if the reused blocks inherit the different power structure in the different location, these blocks cannot be treated as the repeated blocks. So we propose a symmetrical power structure methodology to maintain the power structure in each repeated blocks regardless the floorplan. In this methodology, we create a symmetrical power structure in a floorplan unit. This floorplan unit is a multiple of the Metal2 and Metal1 grid and modifies the initial offset to align the metal grid. Then, in the partition step, we force the partition block's floorplan (shape) to be the multiple of the floorplan unit. In the result, the repeated blocks can be placed in any location and mirror in any axis.
Several Ways to Solve Congestion Issues on Two, Large 65-nanometer (nm) Designs with Magma Author(s): Yang Zhang, Rabby Xiao and Tommy Liu, Texas InstrumentsAbstract: Congestion and routability are major design closure issues hampering today's complex designs at 65nm and below. Congestion affects both the performance (area, timing, power) as well as the yield of the SOC. This paper discribe the analysis of the real congestion problems which we met during two 65nm big designs. Also discribe the reason and solution of these issues. These ways including backend level and also upper levels.
Dealing with Timing Closure Challenges on a 65nm Design Author(s): Tommy Liu, Dell Liang and Yang Zhang, Texas InstrumentsAbstract: Timing closure is the major challenge for current high-speed, complex ASIC design. This paper will not try to address extensive timing closure problems, it will share some experience on one actual 65nm design with magma tools, including the early timing analysis, multi-mode/multi-corner optimze and how to reduce the cycle time of ECO.
Clock Design and Analysis for a 40-nm, 500-MHz DSP CoAuthor(s): Rabby Xiao and Yang Zhang, Texas InstrumentsAbstract: This paper presents a clock tree design method which greatly improve the QOR of Magma cts. This method has been proven to achieve 50ps clock skew across different PTV conditions by driving over 53k flipflops. The method greatly help in reducing clock cycle time and improving tolerance to process variations for high frequency designs in 40nm.
How to Implement 32 LPCAMs in a 65-nm Chip using Magma Author(s): Jinyu Guo, Texas InstrumentsAbstract: LPCAM is different from normal memory. Its size is tall and narrow, Pin count is up to 1024. Other than this, There are some routing blockage on Metal5. It cause severity congestion and bad timing. The paper introduce the method to solve the congestion issue and timing issue using Magma.
Solving Design Challenges Visually with the Talus Visual Volcano Presenter: Magma While IC design complexity increases, engineering teams have remained the same size or have shrunk. Today’s engineers have to be exponentially more productive to get their jobs done. Talus Vortex helps improve designer productivity by delivering improved timing and signal integrity, smaller area, lower power, better manufacturability, faster turnaround time and higher capacity than conventional point-tool flows. But things don’t always go according to plan and schedule. To accelerate design debugging and improve communication between team members, Magma provides the Talus Visual Volcano™. This visual analysis environment integrates and presents all design and analysis data via a common display, allowing you to make better design decisions faster. In this presentation, we’ll show you how the Talus Visual Volcano allows you to:
The Electronic Ocean Presenter: Rajeev Madhavan, CEO, MagmaThe line between analog and digital design is rapidly disappearing as the market for advanced communications, computing and network devices explodes. This “electronic ocean” of mixed-signal functionality marks the beginning of the era of the mixed-signal SoC. Anticipating this trend, Magma embarked on a development effort to bring to market the tools that would be needed to drive the design and implementation of mixed-signal SoCs. The company realized a need to provide best-in-class point-tool solutions that could augment existing flows to solve key design problems in addition to providing full flow solutions. We will cover several of these new best-in-class tools during the keynote. The transition is now complete – Magma is now well-positioned as a leading supplier of mixed-signal SoC design solutions. Biography: Rajeev Madhavan has served as Magma's Chief Executive Officer and Chairman of the Board of Directors since he co-founded the company in 1997, and also served as president until 2001. Madhavan presently serves on the board of directors for the Electronic Design Automation Consortium. Prior to founding Magma, he co-founded and served as President and CEO of Ambit Design Systems, Inc. and co-founded and served as Director of Engineering of LogicVision, Inc. Madhavan received a bachelor's degree in electronics and communication from KREC, Surathkal, India, and a master's degree in electrical engineering from Queen's University, Ontario, Canada.