Jump to content
A Solution to Power Optimization using the Magma UPF Flow Author(s): Muralidhar Naidu, Anurag Mehta and Sudipto Das, Nokia India Pvt. Ltd.Abstract: In this paper we've tried to address the issues that are expected to be solved with the Unified Power Format (UPF) flow. We first present the practical problems faced in a typical non-UPF flow, including extensive manual scripting, hand insertion of special power cells in the design and handling interface issues between various tools across the front end and back end. Next we present our design, a cellular wireless system IP, on which we used the UPF flow. The paper highlights a recommended UPF flow with reference to a typical UPF file and some of the common implementation issues, sources of probable errors and their debugging techniques. Finally we conclude that the UPF flow is indeed a more practical, user friendly and efficient flow across both frontend and backend.
Evaluation of SiliconSmart CCS Library Modeling for Accurate and IR-Drop-Aware Timing Analysis Author(s): Ramakrishnan Subramanian, Priyanko Mitra and Anand Venkitachalam, SanDisk India Abstract: The importance of timing accuracy in sub-micron designs cannot be overstated. Shrinking geometries result in longer interconnects which requires accurate modeling of the drivers. This paper discusses how SiliconSmart® generated composite current source (CCS) libraries addresses the above issue. It demonstrates the CCS library evaluation flow which quantifies the contribution of SiliconSmart in timing accuracy improvement. It compares the accuracy improvement from Nonlinear Delay Model (NLDM) to CCS with an industry-standard SPICE simulator as a reference. It also illustrates the role of SiliconSmart generated CCS libraries in comprehending the IR drop and temperature variation dependence of timing using the V-T scaling capability of the CCS libraries.
Optimal Design Methods for Multi-Voltage Domain, Multimillion-Gate SoCs using Talus GRX, MMMC and CITL Author(s): Prashanth Narayanasetti, Aish Dubey, and Sani Dewal, Texas Instruments Abstract: For large, multi-voltage systems on chip (SoCs) there are two very hard problems to solve. The first problem is at the design planning stage where engineers try to minimize the impact of multiple-power and voltage-domain islands on silicon area. With Talus® 1.1, the new GRX feature allows a high level of flexibility for floorplanning a complex, multi-voltage/multi-power domain SoC. We will discuss QoR comparisons in terms of routing congestion, net detours and quality of repeater insertion for our design, with and without this feature for an SoC with approximately 20 such islands. The second problem is multi-mode timing closure, correlation with respect to the sign-off tool and the related usage models. In this paper, we present a different usage model for a large SoC, where we enable multi-mode/multi-corner (MMMC) and correlation in the loop (CITL) settings post CTS to achieve a good tradeoff between the rate of reduction in timing violations vs. machine runtime.
“Honey, I Shrunk the TAT!!” – Implementation of an Extremely Schedule-Critical 45 nm, Multimillion SoC using Talus 1.1 Author(s): Sharath Chandra, Srinivasa Rangan, Babu Suriamoorthy, Ganesh Sharabu, Suresh Azhagan and Sandeep Premachandran, Qualcomm India Pvt. Ltd Abstract: Despite the fact that 45 nanometer (nm) is now considered a stable technology node and that the EDA industry has evolved to a different dimension in last few years, achieving design closure of 45-nm, multimillion SoC within strict timelines defined by the market demands, still remains a mammoth task. This paper presents some of the key techniques and design practices, which helped us to achieve faster design closure of a 45 nm SoC which has approximately 1.8 million instances: This contribution primarily focuses on the following areas:
This paper also presents our experience with Magma’s multi-corner CTS solution which promises further power and turnaround time benefits.
Early and Efficient Decap and Automatic Power Metal Fill Insertion Using Talus Author(s): Sumanth Poddutur, and Srirai Chellappan, Texas Instruments Abstract: The shrinking technologies, gigahertz range clock frequencies and fabrication rules of today’s SoCs require innovative design techniques. In this paper we discuss the advantages of using Talus to automatically insert decoupling capacitors (decap) and metal fill. Using decap insertion to address dynamic IR-drop issues is fruitful only if they’re placed adjacent to high dynamic power cells. Putting decaps near high power cells after routing, tends to open up congestion/routing/timing problems. We propose an automated way of tackling this problem by creating new down models of all high dynamic power cells such as clock tree buffers, high drive cells and more. These new down models are formed by attaching decaps based on their load driving capability. HyperCells™ for these new down models are created so that they can be sized/placed with decaps considering timing/routing/congestion issues during placement and clock expansion itself and thereby gain on precious back end closure time. Today’s fabrication rules impose minimum/maximum density rules on all metal layers of the SoC. Dummy metal structures, either floating or connected to ground, are added in low-density regions to overcome minimum density rule checks. We will describe a fully automated methodology for utilizing the low-density regions to add power routes and strengthen the power grid. Metal routes are added and converted to the appropriate local power net from within that power domain based on the topography (domain/floorplan/location/metal-layer) or user inputs. This can be customized based on IR-drop results and has been tested successfully on multiple power domain floorplan SoCs. This entire process has been implemented using Talus to eliminate DRC errors.
FineSim Simulation Verification and Performance for Mixed-Signal/Analog Blocks in Complex SoC Designs Author(s): Dillip Routray, Conexant Systems India Pvt. Ltd. Abstract: The Magma FineSim tool is a full-chip circuit-level simulator for design and analysis of analog IPs used in complex mixed-signal SoCs. It contains a full SPICE/fast SPICE engine which has the ability to simulate, utilizing multiple CPUs, with full SPICE-level accuracy. The technology fully caters to analog IPs such as data converters, PLLs and more. This paper presents the simulation methodology and performance of FineSim for simulating DACs/ADCs with their post-annotated netlist. Also, it describes methodology for simulating and analyzing high-speed clock paths for high-speed interfaces. On the basis of these results, the appropriate recommendation can be provided to the physical implementation team for correction of the netlist. All specifications such as SNDR/SFDR/ENOB, pk-pk jitter with package parasitics, DCD and mroe were tried and evaluated with different levels of simulation accuracy. FineSim demonstrated comparable performance with regard to other simulators with considerable speed enhancements.
A Convergent Routing Methodology for High-Performance Designs Author(s): Mohit Parnami, Ramakrishnan Venkatraman, Texas Instruments India Ltd. Abstract: We present a routing methodology that is convergent on timing, while focusing on the basic metrics of congestion and design-rule violations. We analyze aspects of extraction and timing that impact the design quality at various stages of the design flow, show the various variables involved in consistent design closure and their impact, and present a routing methodology that addresses several of these variables. We also highlight recent improvements in the Talus framework that help bridge the gap between timing at global route and the eventual timing at final route. We present results from a high-performance design in a 40-nm technology node. We also present our thoughts on how the methodology can be made generic, to be used across designs, and highlight future improvement areas.
Predictable Timing Closure for Hierarchical Designs using the Talus Flow Manager Author(s): Pinkesh Shah, Open-Silicon Research Pvt. Ltd. Abstract: Timing closure is a growing concern for ASIC designers, particularly with multimillion-gate architectures fabricated at the 90-nm node and below. The Talus® Flow Manager™ (TFM) helped minimize the number of time-consuming place-and-route iterations and provided results that remained stable and predictable across placement, clock tree synthesis and routing across multiple blocks and the top level. In this paper, we describe the usefulness of TFM, ease of use and timing predictability with best achievable correlation with regard to sign-off and turnaround time, given the size of the design and the multi-mode capabilities. Magma's Talus Concurrent Optimization Routing Engine (COre™) engine, powered by TFM optimization capabilities, reduced congestion, turnaround time and yielded an implementation that was much faster and easier to close. We share our experiences of using TFM on a hierarchical design implementation that has 14 million logic gates, approximately 900 memory macros and 20 hierarchical blocks targeted at the 90-nm process, which includes high- speed interfaces like DDR2, SPI4 and Nibble.
Talus Vortex 1.1’s Enhanced Router for 28 nm Author(s): Arun Sundaram, Viji Ranganna, and Bharat Pundi, Engineer, Qualcomm Inc. Abstract: Talus Vortex 1.1 has a new routing technology called eAP “Enhance Access Point” that offers higher quality of results (QoR) and better routability for technologies at 28 nm and below. We used this routing technology to study different library architectures and also for Testchip. eAP has shown a speed increase over the standard router and it delivers high QoR and improved manufacturability. We tested eAP in two ARM9 blocks containing only standard cells of 60K instances and a Vcodec2_serra containing 200K instances and 40 hard macros at different frequencies. With eAP, the routing time was minimal and DRCs were also less and correlated with sign-off tool. Timing also was very good.
Case Study of Efficient Design Closure Methodologies in a Timing-Critical and Highly Congested Multicore, Complex SoC Author(s): Amal Alex, Srinivasulu Alampally and Jaya Singh, Texas Instruments Abstract: In this presentation we will describe some of the key challenges encountered and innovative solutions developed for a highly congested timing critical SoC design. To reduce congestion in highly dense regions, we did timing-slack-based selective spreading of standard cells. We also used novel algorithms to size standard cells based on the available timing slack to achieve maximum impact in reducing congestion. To meet the ARM9 timing of 408MHz, we used innovative region-based optimization and clock management techniques. High congestion and tight schedule goals made ECO convergence very critical. We observed slew degradation due to long nets post detailed route which impacted design timing severely. We used resistance and capacitance of the long nets to determine the right buffering methodology. We also used a novel quadrant-based buffering algorithm to control the slew and reduce the number of buffer additions. We fixed the clock tree during ECO loops to reduce the impact of multiple ECOs.Minimum-Pulse-Width Measurement Methodology Author(s): India Mukul Gupta, Sachin Bapat, and Peeyush Parkar, Qualcomm India, PVT. Ltd Abstract: The intent of developing this new methodology was to find a 3s minimum-pulse-width (MPW) number such that the flops would not go into metastability across process variations. A bisection method was developed that involved the measurement of pulse width when the two internal nodes chosen have transitioned by 80% (for clock) or 95% (for reset/set) at 50% point of clock or reset/set de-assertion. With the recent enhancements, SiliconSmart has the capability of monitoring any number of internal nodes. This gives a better flexibility and robustness for MPW measurement especially for complex cells such as multi-bit registers. The build also has the capability of providing the worst of all possible MPW numbers arising due to different conditions on other inputs.
The Electronic Ocean Presenter: Rajeev Madhavan, CEO, MagmaThe line between analog and digital design is rapidly disappearing as the market for advanced communications, computing and network devices explodes. This “electronic ocean” of mixed-signal functionality marks the beginning of the era of the mixed-signal SoC. Anticipating this trend, Magma embarked on a development effort to bring to market the tools that would be needed to drive the design and implementation of mixed-signal SoCs. The company realized a need to provide best-in-class point-tool solutions that could augment existing flows to solve key design problems in addition to providing full flow solutions. We will cover several of these new best-in-class tools during the keynote. The transition is now complete – Magma is now well-positioned as a leading supplier of mixed-signal SoC design solutions. Biography: Rajeev Madhavan has served as Magma's Chief Executive Officer and Chairman of the Board of Directors since he co-founded the company in 1997, and also served as president until 2001. Madhavan presently serves on the board of directors for the Electronic Design Automation Consortium. Prior to founding Magma, he co-founded and served as President and CEO of Ambit Design Systems, Inc. and co-founded and served as Director of Engineering of LogicVision, Inc. Madhavan received a bachelor's degree in electronics and communication from KREC, Surathkal, India, and a master's degree in electrical engineering from Queen's University, Ontario, Canada.