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User Papers:
Guest Keynote:
Trends and Challenges in Designing Wireless Applications Processor – What is the Need of the Day? Balajee Sowrirajan, Director, IC Engineering, OMAP Business Unit, Texas Instruments India Pvt. Ltd.
Mr. Balajee Sowrirajan has been with Texas Instruments for over 17 years. He was responsible for test CAD tools/ flow development before moving to be part of the wireless seed team in India. He has been leading many activities within the Wireless Business Unit over the past 10 years including digital IP leadership and worldwide SoC management. Currently he is responsible for worldwide IC engineering R&D in the Wireless OMAP Business Unit.
CEO Keynote:Vertically Integrated Product Development: Emerging Silicon Opportunities Rajeev Madhavan, CEO, Magma Design Automation
Faster Last-Mile Closure for Multimillion-Gate SoCs Using Talus MMMC, GRX-Enabled Crosstalk-Aware Route and Optimization Techniques By: Sani Dewal, Ananth Somayaji Goda, Rajiv Girdhar, Anubhav Shukla, Texas Instruments India Pvt. Ltd.
One of the biggest motivations in a SoC execution is faster last-mile closure. In this paper, we highlight the improvements done in this direction. One of knobs which we have developed is to setup a framework for comprehensive correlation of the Talus timer with the sign-off timer. With this, Talus was then used in a MMMC framework to close the remaining violations. This has yielded a major reduction in the final number of violations to work with. In addition, we have used the GRX technology in Talus to get to much better crosstalk-aware routing and have also enabled post-route crosstalk optimization in our flagship product. While this puts tough constraints on the router, we have found the Talus GRX router to be able to converge even on highly complex multimillion-gate and multi-voltage designs like ours. All of this enables a much better starting point for non-functional ECO generation. This has enabled turnaround time improvements on the order of weeks, which is invaluable in the current market conditions.
Talus 1.2: The Look, Feel and Results from a Evaluation Exercise By: Sharath Chandra L, Qualcomm India Pvt. Ltd.
As the semiconductor design houses are diving into the 30- and sub-30-nm node, EDA/CAD teams are working towards enabling the tools for the challenges involved. This paper illustrates the complete execution of a sub-30-nm, approximately 40 mm2 full chip using Talus 1.2 for the complete implementation. The paper highlights what a designer can look for in the new features such as Tekton, robust CTS and MMMC and post-route optimization. The paper also provides the comparison of the runtimes and QoR with the previous Talus version and the benefits that we saw.
FineSim Pro: Fast Circuit Simulator for Efficient IP Development Kartikay Sharma, Nirav Patel, Tejas Gurjar, Prashant Lokeshwar, ARM Inc.
FineSim Pro is a full-chip circuit-level simulator best suited for the design and analysis of mixed- signal SoCs. It contains a full SPICE engine as well as a complete fast-SPICE engine, which provides designers maximum flexibility for accuracy versus speed trade-offs. This paper's intent is to share the benefits FineSim Pro provides to ease the library characterization process while maintaining the accuracy requirements. We also talk about the challenges we faced and the solutions while integrating FineSim Pro into our IP development flow. A brief summary of the results that will be discussed in detail in this paper are as follows: faster than competitor, almost 3x-4x improvement in throughput in the case of standard cells and IOs, ease of configurability, more robust, tight integration with Magma's characterization tool provides further throughput improvement, multi-processor/multi-thread capability, capability to handle circuit checks, static and dynamic IR/EM.
Achieving a Faster Timing-ECO Cycle Using Tekton: A Case Study By: Kiran Kumar, Arun Koithyar, Sinari Vasudev, Texas Instruments India Pvt. Ltd.
In current day SoCs, the effort required for timing ECOs is very significant. So, it is necessary to explore solutions that would help in achieving faster timing-ECO cycles without compromising accuracy. In this paper, we present a case study of using Tekton for timing analysis and faster timing closure. The Tekton timing results are compared against the sign-off tool and the correlation results are presented in this paper. Results of our experiments using Tekton in the timing-ECO cycle are presented. Also, the runtime and CPU resource benefits are discussed. We conclude with the recommendations for the efficient use of Tekton throughout the design life cycle.
Analysis of Clock Jitter in DDR2 Clock Tree and Reduction Techniques Using FineSim By: Senthil Kumar Nagarathinam, Bhanu Prakash, Bhooma Srinivasaraghavan, Qualcomm India Pvt. Ltd.
The clock signal is the most important switching signal for the proper SoC design. The designer must make sure the timing environment is correct. To ensure the signal integrity in clock buffers, jitter becomes the important specification in DDR2-based systems. The variation in transition edges in large circuits is referred as timing jitter. In digital circuits it has been observed that it has high dependency on power supply variation. The power supply variations are termed as dynamic and static respectively in context of this paper. The clock tree network in digital circuits is very sensitive to external noise and designers have a hard time analyzing and reducing timing jitter on the clock. This paper presents a method to analyze clock tree jitter and reduce the clock jitter in the presence of dynamic and static power supply noise using FineSim. Simulations are done at the chip level. Comparative runtime analysis using different simulators is also presented.
An Innovative Approach to Tackle Localized Congestion Using Talus By: Sahidipta Roy, Lokesh Bojan, Netlogic Semiconductor Pvt. Ltd.
With an ever-increasing quest for packing additional functionality on a chip while reducing the available die size, we quite often see localized congestion spots in the design. In this paper we describe a unique and innovative technique employed on a 1M-instance design, at the 40-nm technology node, where we had to face multiple localized congestion spots that arose as a result of the automatic fixing of critical timing paths and ECOs introduced late in the design cycle. We devised a flow wherein we slightly increased the area of every standard cell during placement and recovered the same post placement, thus providing an overall effect of localized cell spreading. It was found that this concept was highly effective in avoiding congestion spots and uniform spreading of the cells. Overall, this approach enabled us to achieve quick design closure with very little congestion and minimal DRC fixing.
MPDR Implementation and Optimization Techniques with Multiple Floorplans for Multi-Domain Low-Power SoCs By: Rivu Das and Arun Koithyar, Texas Instruments India Pvt. Ltd.
It has become a necessity to follow voltage/power domain partitions in modern SoCs for which power and performance are equally important. While it helps in targeted control of power and performance for various SoC use cases, it also brings up key challenges for physical design in terms of arriving at an optimal floorplan and placement optimizations. EDA tools' limitations in handling multiple power domains also throws newer challenges to the designer where optimization of the MPDRs and domain attachments is needed to overcome these limitations. In this paper we explain the issues we faced and the solutions found for the MPDR implementation in an SoC which has fairly complex domain partitions. We present the TFM flow for defining the domains and creating MPDRs, place-and-route care-abouts/methodology, issues and the workarounds used in the flow. We will also discuss various MPDR options tried, merits/demerits of each option and the place-and-route implications.
A Top-Down Approach to Mixed-Signal SoC Verification, Microchip By: Sudarshanam Kommanaboyina, Microchip
The lengthening time required to simulate the entire chip is a major concern in the multimillion- transistor era. Also, waiting for the full-SPICE netlist to get ready and then simulating the full-SPICE netlist to find interface issues at the last stage of the design is more risky. With this traditional flow it is tedious and time consuming to find the interface issues. This presentation covers a traditional flow for simulating ICs which has both analog and digital blocks, at what stage in the design co-sim is preferred over full-SPICE simulations, co-sim flow using FineSim (SPICE netlist) + Modelsim (RTL code) and tools which support co-sim.
Clock Tree Considerations for Improved Quality and Robustness By: Santhosh Thiyagaraja, Vishweshwara Ramamurthy, Venkatraman R., Mahita Nagabhiru, Texas Instruments India Pvt. Ltd.
This paper talks about aspects that impact the clock tree quality and robustness during CTS, issues that are encountered during building clock trees, solutions for a few of those issues and finally improvements needed in the tool to address the shortcomings. Some aspects that affect the clock tree quality are: 1. Clock tree repeater selection - buffers and inverters 2. Optimal cloning and placement of leaf clock gates: Physically aware clock gate cloning placement of clock gates. A custom solution was developed which would reorder the clock sinks across equivalent clock gates and optimize their placement. 3. Floating clusters to help pack the clock gates and the corresponding leaf flops tightly 4. Other CTS strategies, targets for constructing the clock tree etc with Talus We present results on these and talk about other robustness metrics that are of relevance in newer technology nodes, and large chip designs.
Characterization Cycle Time Reduction of Complex DDR IOs Using SiliconSmart ACE By: Sivakumar Jeyaprakash, Qualcomm India Pvt. Ltd.
As the technology advances to deep submicron and further, the complexity involved in the designing the circuits continues to grow. This advancement in the technology also leads to more process variations, which demands the timing closure of the design at more number of process, voltage and temperature (PVT) corners. This introduces huge runtime increases for characterization of DDR IOs. Since the timing specifications for DDR interfaces are very stringent, highly accurate timing models for IOs is required for static timing analysis (STA) of DDR systems. While maintaining the high accuracy it is also important to achieve the design turnaround time so that the STA can be closed for all the design corners. Hence, it is essential to employ techniques which will speed up the simulations without affecting the accuracy. In this paper, the techniques used to reduce the characterization cycle of complex DDR IOs using the SiliconSmart ACE flow without impacting the accuracy of the timing models is presented.
An Efficient Timing Closure Technique for High Performance DSPs and Accelerators with OTB Routing in 40 nm By: Pavan Torvi, Thenappan Meyyappan, Shanthi Rangaswamy, Tilak Wadhwa, Sanjay Singh, Texas Instruments India Pvt. Ltd.
This paper discusses the techniques used to achieve aggressive power, performance and area (PPA) targets in a predictable (and repeatable) timeline for complex DSP (D) and Accelerator (A) blocks. This 40-nm SoC has pushed the envelope for PPA of multiple instantiated D and A blocks! D block has interactions between memories through large LoL (Levels of Logic). In addition, each memory output pin has fanout in the range of 1500. This causes most of the cells in the design to appear in timing critical paths and make area sensitive to timing. The A block has 400 memories and contains an xbar, and the interactions b/n memories is immense. Our objective was to find a sweet spot where all three P, P & A vectors meet. In addition, we wanted to address clock-robustness, dynamic-IR and OTB proactively! Key topics include: synthesis strategy, MMMC scenarios, eCTS approach, bloating and soft grouping, CTS strategy for clock robustness, routing and post-route opt with CCS and correlation to the sign-off tool